• Hardware Support for Software Security
  

  Software bugs, memory corruptions-based attacks and malicious (or natural) at the hardware level can modify either the control flow or the data flow of a program inducing major vulnerabilities. We thus aim at providing hardware-based mechanisms to increase the trust in software execution. With a focus on resource constrained devices used in critical application, the mechanisms are optimized to minimize their footprints but also to be easily integrated at the software level (minimizing or avoiding dedicated software).

  Recent publications in the topic:
  • [TrustFlow] https://ieeexplore.ieee.org/document/8839426)
  • [Lightweight Isolation] https://ieeexplore.ieee.org/document/8893367)
  • [Review of MPU based Isolation Techniques] https://link.springer.com/article/10.1007/s41635-019-00078-6

• Hardware Threat Modeling and Countermeasures Design and Validation:

  Side channel attacks, fault attacks have been proven to be efficient against embedded system security in order to either reveal secret information or to hijack a system. As a result, IC designers and software developers need tools to quickly evaluate their systems against such threats and to validate their countermeasures. Our work aims thus at developing tools to assist hardware designers and software developers in hardware security evaluation. Meantime, we propose optimized countermeasures to overcome such threats.

  Recent publications in the topic:
  • Hardware Security Evaluation Platform
  • [Concurrent Countermeasure] https://ieeexplore.ieee.org/document/8854372 )
    

• System-On Chip and Embedded Systems Life Cycle Security
  

  Trust management through the whole life cycle requires to guarantee the trustworthiness of the device and components but also to manage the stakeholders authentication and access rights (which might change through le life cycle). Physically Unclonable Functions provide valuable hardware primitives to build efficient secure services such authentication schemes. Nevertheless, there are still challenges to address at both hardware and system levels to ease the integration of PUF based security mechanisms. We are notably working on different efficient and robust PUF primitives but also working on the system integration of PUF within secure schemes (from enrollment to use in mission mode).

  Recent publications in the topic:
  • Digital PUF
  • EM IC Authentication

I am teaching the following courses at Grenoble INP Esisar:

• Computer Architecture CE311 : Understand basic components, architecture and use of computer. This course details the key concepts of modern processor architecture and its implications on software and hardware design.
• Digital Design CE211 : Design digital systems on programmable components. Digital design methodology. This course details the key concepts of digital circuit design which are practically applied on FPGA based systems.
• System-on-Chip Design CE514: This course deals with system-on-chip architecture,it details System-on-chip design methodology and key concepts. Software/hardware partitioning issues are discussed and illustrated on a real use case, finally students design and validate their own SystemOnChip based on ARM processor on FPGA.
• Embedded System Design : This course focuses on mcu based embedded system design. Key concept of software programming on MCU are detailed and applied in lab.
• Embedded System Security OS430: This course deals with memory corruption based attacks against software. Countermeasures (either based on hardware or software) to secure applications against such threats are presented (application isolation, control flow integrity…)
• Hardware Security SE515: The course details hardware vulnerabilities of embedded system and digital IC (side channel, fault attacks, counterfeiting, JTAG based attacks …). Evaluation methodology are also dis- cussed. Countermeasures possibly implemented either at the hardware or software level are discussed and studied during labs.

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