David Hély

Latest

• Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing
• The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks
• Towards an Inherently Secure Run-Time Environment for Medical Devices
• A comprehensive hardware/software infrastructure for IP cores design protection
• A red team blue team approach towards a secure processor design with hardware shadow stack
• Centrality Indicators for Efficient and Scalable Logic Masking
• Enhanced Elliptic Curve Scalar Multiplication Secure Against Side Channel Attacks and Safe Errors
• IoT Components LifeCycle Based Security Analysis
• Secure and Flexible Trace-Based Debugging of Systems-on-Chip
• Analysis of laser-induced errors: RTL fault models versus layout locality characteristics
• Clock generator behavioral modeling for supply voltage glitch attack effects analysis
• Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices
• ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes
• From secured logic to IP protection
• High output hamming-distance achievement by a greedy logic masking approach
• How logic masking can improve path delay analysis for Hardware Trojan detection
• Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platform
• On fault injections for early security evaluation vs. laser-based attacks
• On the development of a new countermeasure based on a laser attack RTL fault model
• Reusing logic masking to facilitate path-delay-based hardware Trojan detection
• A secure design-for-test infrastructure for lifetime security of SoCs
• Facilitating side channel analysis by obfuscation for Hardware Trojan detection
• On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks
• Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection
• Secure design-for-debug for Systems-on-Chip
• Validation of RTL laser fault injection model with respect to layout information
• A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks
• Emulation based fault injection on UHF RFID transponder
• Fault tolerance evaluation of RFID tags
• Laser-Induced Fault Effects in Security-Dedicated Circuits
• Laser-induced fault effects in security-dedicated circuits
• On error models for RTL security evaluations
• Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip
• Voltage Glitch Attacks on Mixed-Signal Systems
• An UHF RFID emulation platform with fault injection and real time monitoring capabilities
• Assertion based on-line fault detection applied on UHF RFID tag
• EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement
• Experiences in side channel and testing based Hardware Trojan detection
• Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology
• Run-time detection of hardware Trojans: The processor protection unit
• A physical unclonable function based on setup time violation
• Evaluation of a new RFID system performance monitoring approach
• Malicious key emission via hardware Trojan against encryption system
• RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate
• Read rate profile monitoring for defect detection in RFID Systems
• Towards an unified IP verification and robustness analysis platform
• Protecting an integrated circuit test mode
• Securing Scan Control in Crypto Chips
• A secure scan design methodology
• Secure Scan Techniques: A Comparison
• Test control for secure scan designs
• Scan Design and Secure Chip